A primary design challenge for modern microprocessors, DSPs (digital signal processors), and SoCs (System-on-Chip) in smart phones, tablets, laptops, and servers, etc., is improving power efficiency or performance per Watt. In these clocked synchronous systems, a large percentage of the overall power dissipation is in the clock tree grid and final sequential load. Designing sequential units for low power consumption improve power efficiency of these clocked synchronous systems.
Another knob to reduce power and improve power efficiency in such a system is to lower the supply voltage and scale down frequency. Voltage scaling of a chip may be constrained by the lowest operating voltage (VMIN) under process variation. One of the limiters of VMIN is the sequential hold time degradation at lower voltages resulting in frequency independent functional failures. Since the majority of sequential units have a very low data activity (e.g., 5-10%), clock power dominates the overall sequential dynamic power.
A large percentage of logic paths in a system may have timing slack or are non-critical. Since delay may not be the primary concern, these non-critical paths typically use sequential units with minimum sized transistors to reduce power. These minimum sized sequential units are a common power lever used in many microprocessor and SoC products. These sequential units cannot be downsized any further to take advantage of the timing slack because the sizing of the sequential units depends on the minimum sized transistors allowed by the process technology and that a minimum transistor width is needed to meet the product's VMIN requirements.
One way to reduce power consumption in sequential units is to use pulsed latches. However, pulsed latches degrade hold time and may also suffer pulse width evaporation issues. Another way to reduce power consumption in sequential units is to use auto-gated flip-flops based on data probability. However, for minimum sized flip-flops, power benefit may not be realized for auto-gated flip-flops since the additional gating circuitry consumes more power than saved.